Arithmatic Logic Unit Calculator

• Skills & Tools: Verilog, AMD/Xilinx Vivado, Xilinx FPGA, 7-Segment Display, Digital Logic Design
• Github URL: Project Link
• YouTube Video Demo: Video Link
• Project PowerPoint: Google Slide

This Arithmatic Logic Unit (ALU) Calculator takes three inputs: A - a 4 bit binary number, B - 4 a bit binary number, and Opcode - 4 bit binary number that directs the ALU operations on A and B. The two-digit decimal results were then displayed on the 7-segment FPGA display. The one-digit Opcode was displayed in hexadecimal on the FPGA's left most 7-segment display. Finally, an overflow LED flag and reset button were implemented on the FPGA.

ALU Calculator.v: Serves as the main module utilizing finite state machine (fsm.v), clock_divider.v, binary coded decimal (BCD.v), and decoder.v. It provides computation results for all operations.

Clock Divider.v: Set the clock to oscillate at 1 kHz.

BCD.v: Converted the binary result into 4-bit BCD format (7-segment standard), so results could be displayed elegantly.

FSM.v: Rotates between 3 states at high frequency to display ALU calculator results on the FPGA's 7-segment display. Used decoder file to resolve cathode and anode bit arrays for 7-segment displays.

ALU_tb.v: This was the testbench file, used to simulate the system and generate simulated waveform outputs. This testbench and waveforms were used to ensure the ALU Calculator was functioning as intended prior to synthesis in lab.